VHDL highlighted incorrectly when instantiating component in architecture

The file listed below shows a syntax error (red bold underlined) on the last line of code. However, the code compiles fine with GHDL 3.0 and I cannot find an issue with it. Btw, the Gitlab syntax highlighter below does not take offence either ;-)

The KDE editor component is great, btw! Keep up the good work!

System Info

• Kate Version: 21.12.3
• Operating System: Kubuntu 22.04
• KDE Plasma Version: 5.24.4
• KDE Frameworks Version: 5.92.0
• Qt Version: 5.15.3
• Kernel Version: 5.14.0-1034-oem (64-bit)
• Graphics Platform: X11
• Processors: 12 × Intel® Xeon® W-1250P CPU @ 4.10GHz
• Memory: 31.1 GiB of RAM
• Graphics Processor: Mesa Intel® UHD Graphics P630

VHDL Source

-- Slightly simplified from Ashenden - The Designer's Guide to VHDL,
-- Ch. 13, Figs. 13.10 to 13.12
-- Ignoring the timing generics.
-- Analysis works, elaboration requires a configuration section.
-- Syntax highlighting in KDE Kate fails on `end architecture structural;`

library ieee;
use ieee.std_logic_1164.all;

entity reg is
    generic(
        width: positive
    );
    port(
        clk: in std_logic;
        data_in: in std_logic_vector(0 to width-1);
        data_out: out std_logic_vector(0 to width-1)
    );
end entity reg;

architecture structural of reg is
    component reg is
        generic(
            width: positive
        );
        port(
            clk: in std_logic;
            data_in: in std_logic_vector(0 to width-1);
            data_out: out std_logic_vector(0 to width-1)
        );
    end component reg;
    
    signal clk_ph1: std_logic;
    signal curr_state, next_state: std_logic_vector(0 to width-1);
begin
    state_reg: component reg
        generic map( width => width )
        port map( clk => clk_ph1, data_in => next_state, data_out => curr_state );
end architecture structural;