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Commit 58d00888 authored by Alex Deucher's avatar Alex Deucher
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radeon: pad CS to 8 DW 



Aligns the IB to 8 DWs.  The aligns the IB to the
CP fetch size.  r6xx also require at least 4 DW
alignment to avoid a hw bug.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8a2e0fa9
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